1. Field of the Invention
The present invention relates to the field of semiconductor processing; and more specifically to the field of conditioning methods and apparatuses for polishing pads used in the planarization of thin films formed on a semiconductor substrate.
2. Discussion of Related Art
Integrated circuits (ICs) manufactured today generally rely upon an elaborate system of metallization interconnects to couple various devices which have been fabricated in the semiconductor substrate. The technology for forming these metallized interconnects is extremely sophisticated and well understood by practitioners in the art. Commonly, aluminum or some other metal is deposited and then patterned to form interconnection paths along the surface of the silicon substrate. In most processes a dielectric or insulated layer is then deposited over the first metal (metal 1) layer; via openings are etched through the dielectric layer and the second metallization layer is deposited. The second metal layer covers the dielectric layer and fills the via openings thereby making an electrical contact down to the metal 1 layer. The purpose of this dielectric layer, of course, is to act as an insulator between metal 1 and metal 2 interconnections. Most often the intermetal dielectric layer comprises a chemical vapor deposition (CVD) of silicon dioxide which is normally formed to a thickness of approximately one micron. (Conventionally, the underlying metal 1 interconnections are also formed to a thickness of approximately one micron.) The silicon dioxide layer covers the metal 1 interconnections conformably such that the upper surface of the silicon dioxide layer is characterized by a series of non-planar steps which correspond in height and width to the underlying metal 1 layers.
These step height variations in the upper surface of the interlayer dielectric have several undesirable features. First, non-planar dielectric surfaces interfere with the optical resolution of subsequent photolithography processing steps. This make it extremely difficult to print high resolution lines. A second problem involves a step coverage of metal 2 (second metal) layer over the interlayer dielectric. If the step height is too large there is a serious danger that open circuits will be formed in metal 2 layer.
To combat these problems, various techniques have been developed in an attempt to planarize the upper surface of the interlayer dielectric (ILD). One approach, shown in FIGS. 1a and 1b, employs an abrasive polishing to remove the protruding steps along the upper surface of the dielectric. According to this method a silicon substrate or wafer 102 is forced faced down by quill 103 on a table 104 covered with flat pad 106 which has been coated with an abrasive material (slurry) 108. Both wafer 102 and table 104 are rotated relative to each other under pressure to remove the protruding portions. The abrasive polishing process continues in this manner until the upper surface of the dielectric layer is largely flattened.
Polishing pads 106 of the type used for wafer planarization suffer from a reduction in polishing rate and uniformity due to a loss in sufficient surface roughness. One method of countering the smoothing of polishing pad 106 and achieving and maintaining high and stable polishing rates is pad conditioning. Pad conditioning is the technique whereby the pad surface is put into a proper state for polishing work. This normally entails forming a plurality of microgrooves in the upper polishing pad surface prior to polishing. The microgrooves help to facilitate the polishing process by providing point contacts and by aiding in slurry delivery to the pad/substrate interface. These initially provided grooves, however, become worn or smooth over time necessitating the continual generation of grooves in polishing pad 106 during polishing.
In one conditioning method, shown in FIGS. 1a and 1b and described in U.S. Pat. No. 5,216,843 which is assigned to the present assignee, a multitude of fine microgrooves 110 are formed in the surface of polishing pad 106 with a diamond pointed 112 conditioning block 114. Microgrooves 110 are formed during the polishing process by pivoting diamond conditioning block 114 back and forth across the area 116 of pad 106 which contacts substrate 102. The sweep rate of diamond conditioning block 114 can be varied to condition some parts of the polishing pad 106 more than others (i.e., nonuniformly condition polishing pad 106). Nonuniform conditioning allows those areas of polishing pad 106 which become smoothed to be conditioned more so that the overall roughness of polish pad 106 is uniformly maintained. It is to be appreciated that the polishing rate in this polishing process is proportional to the roughness of the polishing pad (i.e., the amount of conditioning received by the polishing pad). Nonuniform conditioning can improve polish uniformity across the surface of a substrate by maintaining a consistant roughness across the polishing pad.
A problem with conditioning polishing pad 106 with the technique shown in FIG. 1a and 1b, is that although nonuniform conditioning can be achieved with this technique it has been found that its effectiveness is limited. Since conditioning block 114 is rigidly connected to conditioning arm 115, microgroove formation depends on the relative motion of polishing pad 106 and diamond conditioning block 114. In order to increase conditioning of one part of polishing pad 106, the other parts of polishing pad 106 must receive less conditioning. It is to be appreciated that polish rate is proportional to the amount of pad conditioning. In order to nonuniformly condition polishing pad 106 and still maintain a manufacturably acceptable polish rate, it would be necessary to increase the oscillation frequency of diamond conditioning block 114. There is, however, a practical limit (approximately two cycles per second) to oscillation frequency, due to mechanical inertia. Thus, because diamond conditioning block 114 is rigidly attached to conditioning arm 115, nonuniform conditioning of polishing pad 106 can not be obtained without decreasing the overall polish rate. A low polish rate decreases wafer throughput and increases fabrication costs.
Another method for conditioning a polishing pad uses a large diameter diamond particle covered disk (typically about six inches in diameter). In this method the large disk is pressed against the polishing pad and rotated while the polishing pad rotates. One problem with this technique for conditioning a polishing pad is that nonuniform polishing cannot be obtained. Another problem with this technique is the large diameter disk which is used. A large diameter disk has been found unsuitable due to a combination of insufficient surface flatness as well as its inability to track surface variations across the polishing track left in the polishing pad. Such a conditioner tends to gouge portions of the polishing pad while not sufficiently conditioning other portions. Additionally, the grit size and spacing are also difficult to control which has a direct effect on the process and its repeatability disk to disk. Still further, this type of conditioning apparatus easily loses diamond particles which become embedded in the polishing pad and later scratch wafers or substrates. Thus, conditioning with a large diameter rotating disk has been found unsuitable for ultra-large scale integrated circuit (ULSI) manufacturing processes.
Thus, what is required is an improved method and apparatus for conditioning a polishing pad used in semiconductor manufacturing wherein a polishing pad can be nonuniformly conditioned without decreasing the overall polish rate.